december 2011 ?2011 fairchild semiconductor corporation FDZ661PZ rev.c www.fairchildsemi.com 1 FDZ661PZ p-channel 1.5 v specified powertrench ? thin wl-csp mosfet FDZ661PZ p-channel 1.5 v specified powertrench ? thin wl-csp mosfet -20 v, -2.6 a, 140 m features ? max r ds(on) = 140 m at v gs = -4.5 v, i d = -2 a ? max r ds(on) = 182 m at v gs = -2.5 v, i d = -1.5 a ? max r ds(on) = 231 m at v gs = -1.8 v, i d = -1 a ? max r ds(on) = 315 m at v gs = -1.5 v, i d = -1 a ? occupies only 0.64 mm 2 of pcb area. less than 16% of the area of 2 x 2 bga ? ultra-thin package: less than 0.4 mm height when mounted to pcb ? hbm esd protection level > 2 kv (note3) ? rohs compliant general description designed on fairchild's advanced 1.5 v powertrench ? process with state of the art "fine pitc h" thin wlcsp packaging process, the FDZ661PZ minimizes both pcb space and r ds(on) . this advanced wlcsp mosfet embodies a breakthrough in packaging technology which enables the device to combine excellent thermal transfer characte ristics, ultra-low profile (0.4 mm) and small (0.8x0.8 mm 2 ) packaging, low gate charge, and low r ds(on) . applications ? battery management ? load switch ? battery protection bottom top d s s g pin 1 pin 1 wl-csp 0.8x0.8 thin mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage -20 v v gs gate to source voltage 8 v i d -continuous t a = 25 c (note 1a) -2.6 a -pulsed -10 p d power dissipation t a = 25 c (note 1a) 1.3 w power dissipation t a = 25 c (note 1b) 0.4 t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient (note 1a) 93 c/w r ja thermal resistance, junction to ambient (note 1b) 311 device marking device package reel size tape width quantity eh FDZ661PZ wl-csp 0.8x0.8 thin 7 ? 8 mm 5000 units
FDZ661PZ p-channel 1.5 v specified powertrench ? thin wl-csp mosfet www.fairchildsemi.com 2 ?2011 fairchild semiconductor corporation FDZ661PZ rev.c electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = -250 a, v gs = 0 v -20 v bv dss t j breakdown voltage temperature coefficient i d = -250 a, referenced to 25 c -13 mv/c i dss zero gate voltage drain current v ds = -16 v, v gs = 0 v -1 a i gss gate to source leakage current v gs = 8 v, v ds = 0 v 6 a v gs(th) gate to source threshold voltage v gs = v ds , i d = -250 a -0.3 -0.7 -1.2 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = -250 a, referenced to 25 c 2.5 mv/c r ds(on) static drain to source on resistance v gs = -4.5 v, i d = -2 a 108 140 m v gs = -2.5 v, i d = -1.5 a 129 182 v gs = -1.8 v, i d = -1 a 159 231 v gs = -1.5 v, i d = -1 a 201 315 v gs = -4.5 v, i d = -2 a, t j =125c 143 204 g fs forward transconductance v dd = -5 v, i d = -2 a 7.8 s c iss input capacitance v ds = -10 v, v gs = 0 v, f = 1 mhz 416 555 pf c oss output capacitance 61 80 pf c rss reverse transfer capacitance 53 70 pf t d(on) turn-on delay time v dd = -10 v, i d = -2.5 a, v gs = -4.5 v, r gen = 6 4.9 10 ns t r rise time 6.3 13 ns t d(off) turn-off delay time 68 108 ns t f fall time 33 52 ns q g total gate charge v gs = -4.5 v, v dd = -10 v, i d = -2.5 a 6.3 8.8 nc q gs gate to source charge 0.6 nc q gd gate to drain ?miller? charge 1.7 nc v sd source to drain diode forward voltage v gs = 0 v, i s = -1.4 a (note 2) -0.9 -1.2 v t rr reverse recovery time i f = -2.5 a, di/dt = 100 a/ s 29 46 ns q rr reverse recovery charge 10 18 nc notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. the diode connected between the gate and source serves only as protection esd. no gate overvoltage rating is implied. a. 93 c/w when mounted on a 1 in 2 pad of 2 oz copper. b. 311 c/w when mounted on a minimum pad of 2 oz copper.
FDZ661PZ p-channel 1.5 v specified powertrench ? thin wl-csp mosfet www.fairchildsemi.com 3 ?2011 fairchild semiconductor corporation FDZ661PZ rev.c typical characteristics t j = 25 c unless otherwise noted figure 1. 0123 0 2 4 6 8 10 v gs = -1.5 v v gs = -1.8 v v gs = -4.5 v v gs = -3 v v gs = -2.5 v pulse duration = 80 p s duty cycle = 0.5% max -i d , drain current (a) -v ds , drain to source voltage (v) on-region characteristics figure 2. 0246810 0 1 2 3 v gs = -1.5 v v gs = -3 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance - i d , drain current (a) v gs = -2.5 v v gs = -4.5 v v gs = -1.8 v n o r m a l i z e d o n - r e s i s t a n c e v s drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n - r e s i s t a n c e -7 5 - 50 - 25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = -2 a v gs = -4.5 v normalized dr ain t o sou rc e on-resist anc e t j , juncti on temperature ( o c ) vs junction temperature figure 4. 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 150 300 450 600 pulse duration = 80 p s duty cycle = 0.5% max t j = 125 o c t j = 25 o c i d = -2 a r ds(on) , drain to source on-resistance ( m : ) -v gs , gate to source voltage (v) o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 0 0.5 1.0 1.5 2.0 2.5 0 2 4 6 8 10 t j = 25 o c v ds = -5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 150 o c -i d , drain current (a) -v gs , gate to source voltage (v) figure 6. 0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v -i s , reverse drain current (a) -v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDZ661PZ p-channel 1.5 v specified powertrench ? thin wl-csp mosfet www.fairchildsemi.com 4 ?2011 fairchild semiconductor corporation FDZ661PZ rev.c figure 7. 024 68 0 1.5 3.0 4.5 i d = -2.5 a v dd = -12 v v dd = -10 v -v gs , gate to source voltage (v) q g , gate charge (n c) v dd = -8 v gate charge characteristics figure 8. 0.1 1 10 20 10 100 1000 2000 f = 1 mhz v gs = 0 v capacitance (pf) -v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 051 01 5 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 v ds = 0 v t j = 125 o c t j = 25 o c - v gs , gate to source voltage (v) - i g , gate leakage current (a) g a t e l e a k a g e c u r r e n t v s g a t e t o s o u r c e v o l t a g e figure 10. 0.1 1 10 100 0.001 0.01 0.1 1 10 50 this area is limited by r ds(on) 100 us 1 ms 100 ms 1 s dc 10 s 10 ms single pulse t j = max rated r t ja = 311 o c/w t a = 25 o c -i d , drain current (a) -v ds , drain to source voltage (v) forward bias safe
FDZ661PZ p-channel 1.5 v specified powertrench ? thin wl-csp mosfet www.fairchildsemi.com 5 ?2011 fairchild semiconductor corporation FDZ661PZ rev.c figure 12. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 1 2 single pulse r t ja = 311 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a typical characteristics t j = 25 c unless otherwise noted
FDZ661PZ p-channel 1.5 v specified powertrench ? thin wl-csp mosfet www.fairchildsemi.com 6 ?2011 fairchild semiconductor corporation FDZ661PZ rev.c dimensional outlin e and pad layout
7 www.fairchildsemi.com FDZ661PZ p-channel 1.5 v specified powertrench ? thin wl-csp mosfet ?2011 fairchild semiconductor corporation FDZ661PZ rev.c trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporati on, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes wi thout further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fai rchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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